Yes, designing ram is a lower level operation as compared to designing logic via an HDL and needs to directly take the process (chemistry, optics, mechanics) of the fab into account.
Instead of going with the much more expensive SRAM, someone decided that refreshing billions of capacitors hundreds of times a second while performing read and write operations is an acceptable way of storing data (even if only while powered).
I wonder what the managers who first heard the idea must've thought :D
And it works so well! It's probably one of the most reliable component in a computer.
https://openram.soe.ucsc.edu/